1. Technical Field
The present invention relates generally to a semiconductor memory apparatus, and more particularly to a resistive memory apparatus, a layout structure, and a sensing circuit thereof.
2. Related Art
Data stored in a resistive memory apparatus can be read by sensing a current flowing through a memory cell of the resistive memory apparatus during a read operation. The resistive memory apparatus may include a phase change random access memory (PCRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM) and so on. The operation principles of the respective memory apparatuses differ from each other. Nevertheless, a read operation may be understood to be performed in the same manner.
FIG. 1 illustrates a known resistive memory apparatus.
Referring to FIG. 1, the resistive memory apparatus 10 includes a memory cell array 101, a row address decoder 103, a column address decoder 105, a first column selector 107, a second column selector 109, a bit line driver/sinker 111, a source line driver/sinker 113, and a sensing circuit 115. The memory cell array 101 includes a plurality of memory cells coupled between a plurality of bit lines/source lines BL/SL, and a plurality of word lines WL. The row address decoder 103 is configured to drive a word line in response to an external address. The column address decoder 105 is configured to drive the first and second column selectors 107 and 109 in response to an external address. The first column selector 107 is configured to drive a bit line. The second column selector 109 is configured to drive a source line. The bit line driver/sinker 111 is configured to apply a predetermined voltage to the bit line driven by the first column selector 107. The source line driver/sinker 113 is configured to apply a predetermined voltage to the source line driven by the second column selector 109.
When a specific memory cell is enabled by the word line driven by the row address decoder 103, a resistor between a source line and a bit line has a high-level or low-level depending on a resistance state of the memory cell.
During a write operation, that is, when a write enable signal WE is enabled to a high level and a read enable signal RE is disabled to a low level, write circuits such as the bit line driver sinker 111 and the source line driver/sinker 113 operate to drive the selected bit line and source line according to data DATA provided from outside. The resistance of a memory cell selected according to the operation changes to a high or low level.
During a read operation, that is, when the write enable signal WE is enabled to a low level and the read enable signal RE is disabled to a high level, the write circuits such as the bit line driver/sinker 111 and the source line driver/sinker 113 are deactivated, and the sensing circuit 115 is activated. Then, the source line is coupled to a ground terminal, and the bit line is coupled to a sensing node Vc of a sensing unit 1151 included in the sensing circuit 115.
The sensing circuit 115, by using a clamp voltage VCLAMP, does not allow an excessive voltage to be applied to the bit line during a sensing operation. Specifically, a voltage obtained by subtracting a threshold voltage of a switching element N12 from the clamp voltage VCLAMP is applied to the sensing node Vc.
When a memory cell is selected and the sensing circuit 115 is activated during the read operation, the source line becomes coupled to a ground terminal through a switching element 1157 of the sensing circuit 115. Accordingly, a current path (Vc-first column selector-BL-cell-SL-second column selector-ground terminal) is formed between the sensing node Vc and the ground terminal, and current passing through the current path varies depending on the cell resistance.
For example, when the cell resistance is low, a relatively high current IH passes and when the cell resistance is high, a relatively low current IL passes. This current also flows out from a pre-output terminal Pre_out. If it is assumed that bias voltage PBIAS is adjusted so that a current flowing into the pre-output terminal Pre_out has a value between the low current IL and the high current IH during the sensing operation, when the cell resistance value is low, the current flowing out from the pre-output terminal Pre_out becomes larger than the current flowing into the pre-output terminal Pre_out such that the voltage of the pre-output terminal Pre_out decreases. On the other hand, when the cell resistance value is high, the current from the pre-output terminal Pre_out becomes smaller than the current flowing into the pre-output terminal Pre_out such that the voltage of the pre-output terminal Pre_out increases.
Therefore, after a certain time, the cell resistance value can be determined by using a differential amplifier 1153 comparing the voltage of the pre-output terminal Pre_out with a reference voltage REF. That is, when the cell resistance value is low the voltage of the pre-output terminal Pre_out becomes smaller than the reference voltage REF such that output data RD_out becomes low, and when the cell resistance value is high, the voltage of the pre-output terminal Pre_out becomes larger than the reference voltage REF such that the output data RD_out becomes high. The sensed output data RD_out is stored in a latch 1155 and outputted to the outside at a desired time point.
In the sensing circuit 115 illustrated in FIG. 1, in the case of a resistive memory having a small difference in cell resistance value, a sensing margin may become insufficient. In order to secure a sensing margin, the bias voltage PBAIS should be controlled to supply a reference current between two cell currents IL and IH to the pre-output terminal Pre_out. In this case, since a current difference is small and the cell currents are variable, it is difficult to normally perform such a function using the bias voltage PBIAS.
Therefore, the reference current may be generated from a reference cell within a memory cell array and provided to the pre-output terminal Pre_out. This will be described with reference to FIG. 2.
FIG. 2 illustrates another known resistive memory apparatus.
Referring to FIG. 2, the resistive memory apparatus 20 includes a main memory cell array 201A, a reference cell array 201B, a row address decoder 203, a column address decoder 205, a first column selector 207A, a first reference column selector 207B, a second column selector 209A, a second reference column selector 209B, a bit line driver/sinker 211, a source line driver/sinker 213, a first reference driver 215, a second reference driver 217, a reference generation circuit 221, and a sensing circuit 219. The main memory cell array 201A and the reference cell array 201B include a plurality of memory cells coupled between a plurality of bit lines/source lines BL/SL and a plurality of word lines WL. The row address decoder 203 is configured to drive a word line in response to an external address. The column address decoder 205 is configured to drive the first column selector 207A, the first reference column selector 207B, the second column selector 209A, and the second reference column selector 209B in response to an external address. The first column selector 207A is configured to drive a bit line. The first reference qtr column selector 207B is configured to drive a reference bit line. The second column selector 209A is configured to drive a source line. The second reference column selector 209B is configured to drive a reference source line. The bit line driver/sinker 211 is configured to apply a predetermined voltage to the bit line driven by the first column selector 207A. The source line driver/sinker 213 is configured to apply a predetermined voltage to the source line driven by the second column selector 209A. The first reference driver 215 is configured to apply a predetermined voltage to the reference bit line. The second reference driver 217 is configured to apply predetermined voltage to the reference source line.
The resistance memory apparatus 20 of FIG. 2 includes two additional reference cell columns, unlike the resistive memory apparatus 10 of FIG. 1. In this case, high-level data are stored in n reference cells coupled to a reference column RBL0/RSL0, and low-level data are stored in n reference cells coupled to the other reference column RBL1/RSL1.
Before a read operation is started, a write operation for a reference cell is performed. The write operation is performed by the first and second reference drivers 215 and 217 coupled to the reference columns, according to the same manner as a write operation for the main memory cell array 201A.
During the read operation, that is, when a write enable signal WE is enabled to a low level and a read enabled signal RE is disabled to a high level, the operation of the sensing circuit 219 is performed in a similar manner to FIG. 1. In FIG. 2, however, two reference cells are coupled to the reference voltage generation circuit 221 during the read operation, and the reference voltage generation circuit 221 supplies a bias voltage PBIAS for generating a sensing current of the sensing circuit 219 to a sensing unit 2191, and supplies a reference voltage to a comparison unit 2193.
Reference numeral 2197 represents a switching element configured to couple a source line of a selected cell to a ground terminal, and reference numeral 2195 represents a latch configured to store an output signal of the comparison unit 2193.
More specifically, when a word line is activated and the first and second reference column selectors 207B and 209B are activated during the read operation, the reference source lines of two reference cells, that is, cells storing high data and low data are coupled to a ground terminal by a sink unit 2213, and the reference bit lines are coupled to a sensing node Vc through switching elements 123 and N24 of a reference voltage generation unit 2211. At the sensing node Vc, the two reference bit lines are coupled to each other. The voltage of the sensing node Vc corresponds to a voltage obtained by subtracting a threshold voltage of a switching element N21 or N22 from a clamp voltage VCLAMP. Here, a current path is formed through the two reference cells between the sensing node Vc and the ground terminal. Therefore, a high current IH passes through the switching element N23 and a low current IL passes through the switching element N24. These currents are currents flowing from the sensing node Vc, and are equalized to currents flowing from the switching element N21 and the switching element N22 in a normal state. That is, the following relation is established: IN21+IN22=IN23+IN24=IH+IL. However, since the clamp voltage VCLAMP is commonly applied to the gates of the switching elements N21 and N22 and the sensing node Vc is commonly coupled to the sources of the switching elements N21 and N22, the two currents IN21 and IN22 are equalized to each other when the switching elements N21 and N22 operate in a saturation region. That is, the following relation is established: IN21 IN22=(½)*(IH+IL). Furthermore, the current of the switching element N21 is equal to a current of a switching element 121 in a normal state, and is copied into currents of switching elements 122 and P23 by current mirroring of the switching elements P21-P22 and the switching elements P21-P23. That is, the following relation is established: IP21=IP22=IP23=(½)*(IH+IL). The reference voltage generation circuit 221 generates the reference current corresponding to an intermediate value between the two reference cell currents, that is, (½)*(IH+IL), and supplies the reference current to a pre-output terminal Pre_out through the switching element P23 of the sensing circuit 219.
As such, the reference voltage generation circuit 221 stably supplies the reference current between the two reference cell currents, that is, the intermediate current capable of maximizing a sensing margin to the sensing circuit 219, thereby maximizing the sensing margin of the resistive memory having a small cell resistance ratio.
The reference voltage generation circuit 221 also supplies a reference voltage REF. As described above, the current IN22 of the switching element N22 corresponds to (½)*(IH+IL), and the current IP22 of the switching element P22 corresponds to (½)*(IH+IL). Therefore, as the reference voltage REF in a normal state has a value of (½)*VDD, it is possible to acquire a stable reference voltage REF.
The resistive memory apparatus 20 of FIG. 2 may secure a sufficient sensing margin. However, separate circuits for writing data into reference cells, that is, the first and second reference column selectors 207B and 209B and the first and second reference drivers 215 and 217 are required. Accordingly, a separate reference cell write operation should be defined. This is because the reference cells are formed by adding the separate columns.